Basic ~0.5 ns Resolution Event Timing Mechanism
for arrayed muon scintillation detectors

S. Kurowski, 3/97

Application

Measurements of simple muon particle events may be accomplished using an electron photomultiplier tube having a scintillation material over the sensing end of the device to produce Cerenkov radiation when a muon passes through it. The Cerenkov photons then activate the photomultiplier tube, generating a detection event signal. Output events from the tube are binary in nature - the signal amplitude carries no information about the muon. A complete tube and scintillation pane assembly constitute a single muon detector.

Owing to the binary nature of detection events, arraying several such detectors in close proximity can cause a single high-energy muon to pass through more than one detector in series. The geometry of the detector cluster along with the order in which the detectors are penetrated by the muon can be used to discern the particle's direction of motion. (Selection of this geometry and how to extract direction of motion information from the data will be discussed in a separate article.)

The key experimental requirement is the ability to resolve the timing of muon events between detectors in the array. To design for an upper limit we can assume the muons enter the array at about the speed of light, 10⁸ m/sec, or about 3.3 ns/m. If we want to be able to cluster the detectors to within 0.5 m, we will need a timing resolution of at least 1.6 ns.

Description of the Mechanism

Given the above timing requirements and the binary nature of detection events, the easiest way to discriminate the order of detector event triggers is to run a very fast digital clock and as each detector is triggered, it 'snapshots' the value of the clock at that moment, and stores it. The same triggering signals are used to generate a hardware interrupt to an external digital data collection device (say, a PC data port), which then reads the stored snapshot clock values of each detector. This can be done after a comparatively long interval following the actual muon event, at most 2.8 seconds later, but nominally about 50 ms.

The relative differences in the snapshot clock values indicates the serial sequence of detector triggering, and therefor (in conjunction with the detector array geometry) the muon's direction of motion. If the clock is sufficiently fast for the detector separations, the complete velocity vector of the muon can also be determined.

The main advantages of this type of timing mechanism are:

• it is possible for detectors to register simultaneous events without danger of data loss, unlike mutual-exclusion event-order prioritization queues or similar mechanisms,
• the system is completely digital, allowing easy data collection using off-the-shelf PC hardware,
• state of the art Emitter-Coupled-Logic (ECL) ICs operate right about the 1 GHz range, some slightly faster.

Below is a rough diagram outlining an example implementation of this clocking and snapshot mechanism.

If we assume muon events are likely to be very close together in time (<< 1sec) a 1.5GHz clock can be counted by 4 staged 8-bit fast ECL counters, the carry bit of the last counter stage being used to reset all 4 stages (or simply left floating - it should not matter). This forms a 32-bit counter that starts at 0 and rolls over from 2³²-1 back to 0 again every 2.8 seconds. (ECL counters also exist for 4 GHz rates.) Since we never expect associated muon events 2.8 seconds apart, the value of this counter can be considered unique for any one detection event, with counter values differing by between 0 and perhaps 4, of course depending upon the detector separation distances.

The storing of the clock counter value is accomplished by latching the state of the four (4x) 8-bit counter outputs using eight (8x) 4-bit ECL latches. These latches are somewhat slower than the counters, requiring about 500 ps to acquire and hold. At this point in the design of this mechanism, this is the main constraining factor. Faster latches would enable us to use a faster clock counter to achieve even better timing resolution, down to perhaps 10 cm between detectors.

The clock counters share their values on a 32-bit wide bus, the connections to which must all be of equal length. There is a separate group of ECL latches for each detector. A single (differentiated transition-conditioned) event pulse from the detector causes its latch group to store the clock count value at that moment. A second 32-bit wide bus exports the stored clock value for the detector and can be read more or less continuously.

The 32-bit output bus is multiplexed (not shown) by a selection address from the remote data collection device. This specifies which detector's event group is to have its clock value presented on the output port to the PC. The minimum number of pins required for the PC connector for up to 16 arrayed detectors is 32[data] + 4[detector select] + 1[gnd] + 16[event trigger] = 53 pins. It is possible to divide the control lines (detector select, event trigger) from the data lines for two different PC ports.

Operating this device at a 1.5 GHz clock rate should be able to resolve event timing as tightly as the ECL latches permit, about 0.5 ns, translating to a detector separation of about 15 cm.

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